2 results for Bedi, Abhishek, Masters

  • A generic platform for the evolution of hardware

    Bedi, Abhishek (2009-06-15T00:56:03Z)

    Masters thesis
    Auckland University of Technology

    Evolvable Hardware is a technique derived from evolutionary computation applied to a hardware design. The term evolutionary computation involves similar steps as involved in the human evolution. It has been given names in accordance with the electronic technology like, Genetic Algorithm (GA), Evolutionary Strategy (ES) and Genetic Programming (GP). In evolutionary computing, a configured bit is considered as a human chromosome for a genetic algorithm, which has to be downloaded into hardware. Early evolvable hardware experiments were conducted in simulation and the only elite chromosome was downloaded to the hardware, which was labelled as Extrinsic Hardware. With the invent of Field Programmable Gate Arrays (FPGAs) and Reconfigurable Processing Units (RPUs), it is now possible for the implementation solutions to be fast enough to evaluate a real hardware circuit within an evolutionary computation framework; this is called an Intrinsic Evolvable Hardware. This research has been taken in continuation with project 'Evolvable Hardware' done at Manukau Institute of Technology (MIT). The project was able to manually evolve two simple electronic circuits of NAND and NOR gates in simulation. In relation to the project done at MIT this research focuses on the following: To automate the simulation by using In Circuit Debugging Emulators (IDEs), and to develop a strategy of configuring hardware like an FPGA without the use of their company supplied in circuit debugging emulators, so that the evolution of an intrinsic evolvable hardware could be controlled, and is hardware independent. As mentioned, the research conducted here was able to develop an evolvable hardware friendly Generic Structure which could be used for the development of evolvable hardware. The structure developed was hardware independent and was able to run on various FPGA hardware’s for the purpose of intrinsic evolution. The structure developed used few configuration bits as compared to current evolvable hardware designs.

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  • A colour segmentation method for detection of New Zealand speed signs

    Bedi, Abhishek (2011-11-29)

    Masters thesis
    Auckland University of Technology

    New Zealand Speed signs provide safe travelling speed limit or guidance information to drivers on roads. The speed signposts are provided alongside the national roads and highways as a part of guidance system for drivers and are entrenched by the New Zealand Transport Agency (NZTA). The speed limit in New Zealand is decided by the speed limits policy of NZTA. The objective of speed limits policy is to balance the interests of mobility and safety by ensuring speed limits are safe, appropriate and credible for the level of roadside development and the category of road for which they are set. In New Zealand, speed limits may be temporary, changing kilometre by kilometre or hour to hour. The research undertaken is to develop a commercially effective NZ Speed sign recognition system to be used at Geosmart NZ Ltd. Geosmart (NZ) Ltd is New Zealand's geospatial solutions provider. The current system being used to determine the speed signs is a manual system, where a human input is required to observe terabytes of data. To speed up the process and get accurate information, the company requires an automated system to detect changes in the speed limits in short interval of time at different areas on the country’s roads. This research will aim at finding an efficient solution for recognition of NZ based road signs in software, especially when the speed signs are located in dark or gloomy images. This research proposes a new method to treat images with low level lighting conditions during the process of colour segmentation, a method used in digital image processing.

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