14 results for Pearson, Murray W.

  • Parallel programming with PICSIL1

    Pearson, Murray W.; Melchert, Matthew (1993-10)

    Working or discussion paper
    University of Waikato

    This paper describes the background and development of PICSIL1 a visual language for specifying parallel algorithms using structured decomposition. PICSIL1 draws upon graphical and textual specification techniques; the first for high level structure of an algorithm, the second for more detailed functional specifications. The graphical specification techniques used in PICSIL1 are based on Data Flow Diagrams (DFDs) and are well suited to the assembly and interconnection of abstract modules. Minor modifications to DFDs have however had to be made to make them suitable for describing parallel algorithms. These include the ability to dynamically replicate sections of a diagram and change the structure of parts of a diagram dependent on data being processed. Work is proceeding on the development of an editor to allow the direct capture and editing of PICSIL1 descriptions. In the near future development of compiler and visual debugging tools are planned.

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  • PICSIL: integrating graphic system design and automatic synthesis

    Pearson, Murray W.; Lyons, Paul J.; Apperley, Mark (1995-01)

    Working or discussion paper
    University of Waikato

    We present an approach to the design of complex logic ICs, developed from four premises. First, the responsibilities of a chip's major components, and the communication between them, should be separated from the detailed implementation of their functionality. Design of this abstract architecture should precede definition of the detailed functionality. Secondly, graphic vocabularies are most natural for describing abstract architectures, by contrast with the conventional textual notations for describing functionality. Thirdly, such information as can be expressed naturally and completely in the idiom of the abstract architecture should be automatically translated into more complex, lower-level vocabulary. Fourthly, the notations can be integrated into a single, consistent design-capture and synthesis system. PICSIL is a preliminary implementation of a design environment using this approach. It combines an editor and a synthesis driver, allowing a design's abstract architecture to be created using a graphical notation based on Data Flow Diagrams and state machines, and its functionality to be designed using a more conventional textual hardware description language. On request, it also translates a design into appropriate input for synthesis software, and controls the operation of that software, producing CIF files suitable for fabrication. Thus computer systems become appropriate for ab initio design production rather than post facto design capture.

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  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-07)

    Working or discussion paper
    University of Waikato

    No. 94/11 (replaced by 94/16)

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  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-09)

    Working or discussion paper
    University of Waikato

    The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable instructions and memory accesses are time stamped. The TimeWarp algorithm is used for managing synchronisation. This algorithm is optimistic and requires that all computations can be rolled back. The basic functions required for implementing the control and memory system used by TimeWarp are described. The memory model presented to the programmer is a single linear address space modified by a single thread of control. Thus, at the software level there is no need for explicit synchronising actions when accessing memory. The physical implementation, however, is multiple CPUs with their own caches and local memory with each CPU simultaneously executing multiple threads of control.

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  • High performance simulation for ATM network development

    Cleary, John G.; Pearson, Murray W.; Graham, Ian; Unger, Brian (1996-06)

    Working or discussion paper
    University of Waikato

    Techniques for measuring and modeling ATM traffic are reviewed. The requirements for cell level ATM network modeling and simulation are then outlined followed by a description of an ATM traffic and network (ATM-TN) simulator. This ATM-TN simulator is built upon parallel simulation mechanisms to achieve the high performance needed to execute the huge number of cell events required for a realistic network scenario. Results for several simulation experiments are reported using this high performance simulation including scenarios for the Wnet and OPERA networks. Finally, a preliminary evaluation of the application of high performance simulation to the design and analysis of ATM network performance is provided.

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  • Current techniques for measuring and modeling ATM traffic

    Pearson, Murray W.; Cleary, John G.; Unger, Brian; Williamson, Carey (1996-06)

    Working or discussion paper
    University of Waikato

    ATM has now been widely accepted as the leading contender for the implementation of broadband communications networks (Brinkmann, Lavrijsen, Louis, et al, 1995) ATM networks are no longer restricted to research laboratories, and commercial products such as switches and interfaces manufactured by well known computer and communications companies have started to appear in the market place. The main advantage seen in ATM over other broadband networking technologies such as Synchronous Transfer Mode (STM) is its ability to transmit a wide variety of traffic types, including voice, data and video efficiently and seemlessly.

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  • Design of a processor to support the teaching of computer systems

    Pearson, Murray W.; Armstrong, Dean Andrew; McGregor, Anthony James (2002)

    Conference item
    University of Waikato

    Teaching computer systems, including computer architecture, assembly language programming and operating system implementation, is a challenging occupation. At the University of Waikato this is made doubly true because we require all computer science and information systems students study this material at second year. The challenges of teaching difficult material to a wide range of students have driven us to find ways of making the material more accessible. The corner stone of our strategy for delivering this material is the design and implementation of a custom CPU that meets the needs of teaching. This paper describes our motivation and these needs. We present the CPU and board design and describe the implementation of the CPU in an FPGA. The paper also includes some reflections on the use of a real CPU rather than a simulation environment. We conclude with a discussion of how the CPU can be used for advanced classes in computer architecture and a description of the current status of the project.

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  • Constraints on parallelism beyond 10 instructions per cycle

    Cleary, John G.; Littin, Richard H.; McWha, David J.A.; Pearson, Murray W. (1997-11)

    Working or discussion paper
    University of Waikato

    The problem of extracting Instruction Level Parallelism at levels of 10 instructions per clock and higher is considered. Two different architectures which use speculation on memory accesses to achieve this level of performance are reviewed. It is pointed out that while this form of speculation gives high potential parallelism it is necessary to retain execution state so that incorrect speculation can be detected and subsequently squashed. Simulation results show that the space to store such state is a critical resource in obtaining good speedup. To make good use of the space it is essential that state be stored efficiently and that it be retired as soon as possible. A number of techniques for extracting the best usage from the available state storage are introduced.

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  • Improving the performance of HTTP over high bandwidth-delay product circuits

    McGregor, Anthony James; Pearson, Murray W.; Cleary, John G. (2001)

    Conference item
    University of Waikato

    As the WWW continues to grow, providing adequate bandwidth to countries remote from the geographic and topological center of the network, such as those in the Asia/Pacific, becomes more and more difficult. To meet the growing traffic needs of the Internet some Network Service Providers are deploying satellite connections. Through discrete event simulation of a real HTTP workload with differing international architectures this paper is able to give guidance on the architecture that should be deployed for long distance, high capacity Internet links. We show that a significant increase in the time taken to fetch HTTP requests can be expected when traffic is moved from a long distance international terrestrial link to a satellite link. We then show several modifications to the network architecture that can be used to greatly improve the performance of a satellite link. These modifications include the use of an asymmetric satellite link, the multiplexing of multiple HTTP requests onto a single TCP connection and the use of HTTP1.1.

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  • An overview of link-level measurement techniques for wide-area wireless networks

    Raynel, Scott; Pearson, Murray W. (2008)

    Conference item
    University of Waikato

    By building wireless link-level measurement tools we hope to improvement the design, deployment and management of wide-area wireless community networks. This paper identifies existing link-level measurement techniques and discusses the advantages and disadvantages of each in the context of measuring and monitoring such networks. Finally, we make a case for the need for more sophisticated techniques and tools which will assist both day-to-day network operations as well as wireless network research.

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  • Measuring ATM traffic: final report for New Zealand Telecom

    Cleary, John G.; Graham, Ian; Pearson, Murray W.; McGregor, Anthony James (1998-10)

    Working or discussion paper
    University of Waikato

    The report describes the development of a low-cost ATM monitoring system, hosted by a standard PC. The monitor can be used remotely returning information on ATM traffic flows to a central site. The monitor is interfaces to a GPS timing receiver, which provides an absolute time accuracy of better than 1 µsec. By monitoring the same traffic flow at different points in a network it is possible to measure cell delay and delay variation in real time, and with existing traffic. The monitoring system characterises cells by a CRC calculated over the cell payload, thus special measurement cells are not required. Delays in both local area and wide-area networks have been measured using this system. It is possible to measure delay in a network that is not end-to-end ATM, as long as some cells remain identical at the entry and exit points. Examples are given of traffic and delay measurements in both wide and local area network systems, including delays measured over the Internet from Canada to New Zealand.

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  • High-level graphical abstraction in digital design

    Pearson, Murray W.; Lyons, Paul J.; Apperley, Mark (1996)

    Journal article
    University of Waikato

    We base our approach to the design of complex logic ICs on four premises: Design of a chip's abstract architecture—its major components, their tasks, and their intercommunication—should precede definition of its functionality. Graphics is ideal for representing abstract architectures; text is better for functionality. The designer should not have to translate graphical information into text. Graphical and textual design capture can be integrated with synthesis. © 1996, OPA (Overseas Publishers Association) Amsterdam B.V.

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  • Wireless local area network planning: an overview

    Bartels, Samuel James; Pearson, Murray W. (2008)

    Conference item
    University of Waikato

    When planning a wireless local area network, there are design issues that need to be considered. In this paper, the fundamentals of planning a wireless local area network are introduced and discussed to highlight the requirements involved. Network constraints, as their relevance to wireless network design is investigated. The paper concludes with an overview of wireless network planning solutions including commercial and free software, and an introduction to the author’s research.

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  • High precision traffic measurement by the WAND research group

    Cleary, John G.; Graham, Ian; McGregor, Anthony James; Pearson, Murray W.; Siedins, Ilze; Curtis, James; Donnelly, Stephen; Martens, Jed; Martin, Stele (1999-12)

    Working or discussion paper
    University of Waikato

    Over recent years the size and capacity of the Internet has continued its exponential growth driven by new applications and improving network technology. These changes are particularly significant in the New Zealand context where the high costs of trans-Pacific traffic has mandated that traffic be charged for by volume. This has also lead to a significant focus within the New Zealand Internet community on issues of caching and of careful planning for capacity. Approximately three years ago the WAND research group began with a program to measure ATM traffic. We were sharply constrained by cost and decided to start by reprogramming some ATM NIC cards. This paper is largely based on our experience as we have broadened this work to include IP-based non-ATM networks and the construction of our own hardware. We have learned a number of lessons in this work, rediscovering along the way some of the hard discipline that all observation scientists must submit to.

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