2 results for Working or discussion paper, The architecture of an optimistic CPU: the WarpEngine

  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-07)

    Working or discussion paper
    University of Waikato

    No. 94/11 (replaced by 94/16)

    View record details
  • The architecture of an optimistic CPU: the WarpEngine

    Cleary, John G.; Pearson, Murray W.; Kinawi, Husam (1994-09)

    Working or discussion paper
    University of Waikato

    The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable instructions and memory accesses are time stamped. The TimeWarp algorithm is used for managing synchronisation. This algorithm is optimistic and requires that all computations can be rolled back. The basic functions required for implementing the control and memory system used by TimeWarp are described. The memory model presented to the programmer is a single linear address space modified by a single thread of control. Thus, at the software level there is no need for explicit synchronising actions when accessing memory. The physical implementation, however, is multiple CPUs with their own caches and local memory with each CPU simultaneously executing multiple threads of control.

    View record details